More cores. Fewer threads. A quarter fewer, to be exact.
At Computex 2026 in Taipei, Intel unveiled Diamond Rapids, a 192-core Xeon processor that marks both an architectural leap and a quiet retreat — abandoning Hyperthreading after twenty-four years even as it adds cores, yielding a net reduction in thread count. The move signals Intel's belated embrace of the chiplet design philosophy AMD pioneered, suggesting that the server processor wars are no longer about who innovates first, but who executes best. With AMD's 256-core Venice Epycs potentially arriving a full year earlier, Diamond Rapids arrives as a statement of intent shadowed by the question of whether intent alone is enough.
- Intel's headline number — 192 cores, a 50% increase — is immediately complicated by the removal of Hyperthreading, leaving customers with 25% fewer threads than the core count implies.
- The disappearance of SMT after 24 years creates real economic disruption in virtualized environments, where licensing is tied to thread counts and vendors like VMware and Red Hat would need to restructure how they sell.
- Intel's adoption of AMD-style chiplet architecture, stacking compute dies atop shared I/O and cache layers, signals a fundamental concession that its monolithic design era is over.
- AMD's Venice Epycs at 256 cores may reach the market a full year before Diamond Rapids ships in 2027, turning Intel's announcement into a race it is already running from behind.
- Intel's own roadmap undermines the decision — the successor chip, Coral Rapids, will restore SMT, framing Diamond Rapids less as a strategic pivot and more as an awkward detour.
Intel took the stage at Computex 2026 in Taipei with Diamond Rapids, a Xeon processor carrying 192 cores — fifty percent more than its predecessor. The headline, however, came with a catch: Intel has removed Hyperthreading entirely, the simultaneous multithreading technology it has shipped since 2002. The arithmetic is counterintuitive. More cores, but a quarter fewer threads.
Hyperthreading was built on a simple insight — processors have idle moments, and a second thread can fill those gaps without adding silicon. It never doubled performance, but for many workloads it delivered meaningful gains. Its removal from Diamond Rapids follows its earlier exit from Intel's consumer chips, yet the decision appears to be temporary. Intel's next chip after Diamond Rapids, Coral Rapids, will bring SMT back — making this look less like a strategic shift and more like a costly detour.
The architecture beneath the controversy is more coherent. Intel has adopted the chiplet design AMD pioneered, assembling Diamond Rapids from separate silicon pieces rather than a single monolithic die. Two I/O dies sit atop four stacked compute assemblies, each carrying 48 cores, all bound by Intel's Foveros packaging. The L3 cache migrates to a base die — a space-saving technique Intel used in Clearwater Forest and one that mirrors Fujitsu's Monaka design. Intel is no longer contesting AMD's architectural philosophy; it is following it.
The competitive picture remains difficult. AMD's Venice Epycs will reach 256 cores and may arrive a full year before Diamond Rapids, which Intel now targets for 2027. Intel has positioned Diamond Rapids for high-performance computing and demanding cloud infrastructure rather than mainstream deployment — a framing that sidesteps, but does not resolve, the licensing complications that arise when virtualization vendors charge per thread.
Diamond Rapids will ship with sixteen channels of DDR5 memory, delivering roughly 1.2 terabytes per second of bandwidth per socket — territory that matters deeply in HPC. Key details including power consumption and per-clock efficiency gains remain undisclosed until Intel presents at Hot Chips in August. Until then, Diamond Rapids is a processor defined as much by what it surrendered as by what it gained.
Intel walked onto the Computex stage in Taipei this week with a processor that looks, on paper, like a decisive move forward. The Diamond Rapids Xeon will pack 192 cores—a fifty percent jump from the generation before it. But the company also made a choice that undercuts that headline: it has removed Hyperthreading entirely, the simultaneous multithreading technology Intel has been shipping since 2002. The result is counterintuitive. More cores. Fewer threads. A quarter fewer, to be exact.
Hyperthreading was always Intel's answer to a simple problem: silicon has idle moments. While a processor executes one instruction, parts of it sit unused. SMT lets a second thread slip into those gaps, harvesting work that would otherwise be wasted. It doesn't double throughput—nothing is that clean—but for certain workloads it can deliver gains in the double digits. For twenty-four years, it was a standard feature. Now it's gone from the Xeon line, following its quiet exit from Intel's consumer chips.
But Intel appears to have already reconsidered. The company's next processor after Diamond Rapids, codenamed Coral Rapids, will bring SMT back. The decision to remove it from Diamond Rapids, then, reads less like a permanent shift and more like a detour—one that complicates the picture for customers trying to understand what they're actually buying.
The architecture underneath tells a different story. Intel has adopted the chiplet approach that AMD pioneered years ago, stitching together separate pieces of silicon rather than building one monolithic die. Diamond Rapids will use Intel's 18A-P process, a refinement of its 2-nanometer class technology, and from the renderings Intel shared, the design looks like this: two input-output dies sitting atop four vertically stacked compute assemblies, all bound together using Intel's Foveros packaging. Each compute chiplet will carry 48 cores. The L3 cache moves to a base die, freeing up real estate on the compute pieces themselves—a trick Intel has used before with Clearwater Forest, and one that mirrors the design Fujitsu used for its Monaka processor.
This matters because it shows Intel is no longer fighting AMD's architectural choices. It's copying them. The 192-core count, while substantial, still trails AMD's Venice Epycs, which will hit 256 cores. Worse, AMD may reach the market a full year before Diamond Rapids ships, which Intel now targets for 2027.
Diamond Rapids is not being positioned as a mainstream part. Intel has classified it as optimized for high-demand cloud infrastructure and high-performance computing—the same category as its existing 6900P-series processors. That positioning matters because it sidesteps some of the licensing complications that come with removing SMT. In virtualization, where hypervisors typically charge per thread, losing a quarter of your thread count is a significant economic hit. Oracle worked around this with its Ampere-based instances by renting cores in pairs rather than individually, but that required special arrangements. Diamond Rapids customers would need similar buy-in from vendors like VMware or Red Hat.
The chip will ship with sixteen channels of DDR5 memory—far more bandwidth than most workloads need, but exactly what HPC applications demand. Intel hasn't disclosed final memory speeds, but given that Clearwater already supports 8000 MT/s and Granite could reach 8800 MT/s, assuming 9600 MT/s is reasonable. That translates to roughly 1.2 terabytes per second of bandwidth per socket, matching what Nvidia's Vera CPUs deliver. Power consumption and instruction-per-clock improvements remain undisclosed, details Intel will likely reveal in August when it presents at Hot Chips. Until then, Diamond Rapids remains a processor defined by what it gained and what it gave up—and by the question of whether that trade was worth making.
Notable Quotes
Diamond Rapids is optimized for high-demand IaaS and high-performance computing workloads, not mainstream enterprise virtualization or storage servers.— Intel
The Hearth Conversation Another angle on the story
Why would Intel remove Hyperthreading now, when core counts are climbing? Doesn't that seem backward?
It does on the surface. But Diamond Rapids is built for HPC workloads, not general-purpose servers. Those applications are often thread-limited by memory bandwidth or compute density, not by thread count. Removing SMT lets Intel simplify the core design and pack more of them onto the die.
But they're bringing it back in the next generation. So what was the point?
That's the real question. It might have been a trade-off they felt forced to make at 18A-P, or it could be that they wanted to see how the market reacted. Either way, it signals uncertainty about the direction.
How does this compare to what AMD is doing?
AMD's Venice Epycs go to 256 cores and keep their threading intact. They're also likely to ship first. Intel is playing catch-up on core count and architecture both.
Does the chiplet design change how these processors actually work?
Not fundamentally. It changes how they're built and how data flows between pieces. The L3 cache on the base die means compute chiplets don't waste space on it. It's efficient, but it's also what AMD figured out years ago.
So Intel is following AMD's playbook now?
In architecture, yes. But they're still ahead on process technology. The question is whether that advantage matters if AMD ships first and hits higher core counts.