Intel Nova Lake Compute Tile Swells to 150mm² With Massive L3 Cache Expansion

Intel's next generation of desktop processors, expected to arrive late this year or early next year under the Core Ultra 400 branding, is shaping up to be a significant departure from the company's current lineup. The immediate problem Intel is trying to solve is straightforward: gamers have largely rejected the current generation of chips, and the company knows it. One of the most direct ways to address that weakness, according to emerging leaks, is to dramatically expand the L3 cache—tripling or even quadrupling what exists today.

A recent leak from hardware observer HXL suggests Intel's approach to this cache expansion will be different from what AMD is doing. Rather than stacking additional cache above or below the main compute tile, Intel appears to be integrating the expanded cache directly into the tile itself. The numbers tell the story: a standard Nova Lake compute tile would measure around 110 square millimeters, but a version with the expanded cache—what the industry calls "bLLC" or big Last Level Cache—would balloon to approximately 150 square millimeters. That's a 36 percent increase in die area, a substantial jump that reflects the sheer volume of additional cache being added to the chip.

To understand why this matters, it helps to look at what Intel is working with. The company's current compute tile is already quite large by historical standards. Earlier estimates from other leakers put it at 96 square millimeters. For comparison, AMD's upcoming Zen 6 core complex—a twelve-core design—is expected to measure around 76 square millimeters. The size difference is striking, especially when you consider that Intel's Nova Lake is rumored to pair eight performance cores with four efficiency cores, a configuration that should theoretically be comparable in complexity to AMD's twelve-core design. Yet Intel's approach is consuming considerably more silicon.

The cache configuration itself reveals Intel's strategy. Each pair of performance cores is said to share a 4-megabyte L2 cache, double what the previous generation offered. AMD is reportedly moving in a similar direction with Zen 6, potentially doubling its L2 cache to 2 megabytes per core. On paper, the two approaches look aligned. In practice, Intel's overall die footprint suggests the company is making different trade-offs in how it's organizing and implementing these caches.

What makes the 150-square-millimeter figure particularly striking is the context. That's the size of an entire system-on-chip from Intel's Tiger Lake laptop processors. But the 150-square-millimeter compute tile is just one piece of Nova Lake. The complete processor also requires an SoC tile, an I/O tile, a dedicated Xe3P GPU tile, and a base tile that ties everything together using Intel's Foveros Advanced packaging technology. The compute tile alone, in its largest configuration, occupies as much silicon as a complete mobile processor from just a few years ago.

Die area is a peculiar specification in the semiconductor world. It's nearly invisible to end users—no one buys a processor because it's a certain number of square millimeters. But for manufacturers and analysts, it's a window into the design process and a signal about what a chip will cost to produce. Larger dies mean fewer chips per wafer, which means higher per-unit manufacturing costs. If Intel is indeed committing to compute tiles this large, the company will need to deliver genuinely compelling performance gains to justify the expense. The gaming weakness in current-generation chips is real, and the market is waiting to see whether this aggressive expansion of cache will be enough to win back customers who have turned to AMD. If the leaked numbers are accurate, Nova Lake's pricing will likely reflect the substantial silicon investment required to build it.