Every chip sits in someone's hands eventually, and that is where a quieter kind of danger begins: an adversary who can pick up the silicon, probe its underside, and try to bend it to their purpose. AMD has answered that old worry with the Versal TR line, a family that folds physical protection into the silicon itself rather than leaving it to custom enclosures and bespoke board-level defences. It is a bet that the people guarding defence systems, infrastructure and financial networks would rather trust the chip than build fortresses around it, and the test of that bet lies a year or more ahead
AMD Unveils Versal TR Chips With Built-In Protection Against Physical Backside Attacks
If the protection die is tampered with or removed, the chip will not boot.
Mark
So what is actually new here? Chips have had security features for years.
Mimi
The backside protection. A sensor die is bonded to the main die and covers the whole back of the device. If someone removes or tampers with it, the chip won't boot.
Mark
Why does that matter to a buyer?
Mimi
Today many organisations build their own protection from enclosures, custom chips and board-level measures. That adds cost and design complexity. AMD wants to move some of that into the silicon.
Luke
Worth noting that "first" is AMD's own claim, and the protection claims are the company's description. The source offers no independent testing.
Mark
The glitch detection and post-quantum pieces seem like a separate story.
Mimi
They're additions. There's support for two post-quantum signature algorithms, a hybrid boot flow, a key vault update and an aging sensor for key safeguards. The glitch detector now covers simultaneous glitches on two voltage rails.
Luke
Again, those are features listed, not results demonstrated. We don't know how they perform against real attackers.
Mark
And the migration angle?
Mimi
Each TR part has a footprint-compatible standard counterpart. Customers can start on those and move later without rerunning synthesis or place and route.
Luke
Also the performance numbers are "up to" figures, and nothing is on sale yet. Sampling is second half of 2027, production first half of 2028. Pricing isn't mentioned at all.
El Pulso
- A chip that refuses to boot if its protective layer is touched or removed turns the device itself into an alarm.
- Organisations guarding defence, infrastructure and finance have long piled custom shielding onto boards, and AMD is offering to replace that effort with one integrated answer.
- Standard counterparts with matching footprints let developers start building now and switch to the hardened parts later without redoing synthesis or place and route.
- Samples are slated for the second half of 2027 and production for the first half of 2028, leaving the market to decide whether the integrated approach wins over familiar workarounds.
Every chip sits in someone's hands eventually, and that is where a quieter kind of danger begins: an adversary who can pick up the silicon, probe its underside, and try to bend it to their purpose. AMD has answered that old worry with the Versal TR line, a family that folds physical protection into the silicon itself rather than leaving it to custom enclosures and bespoke board-level defences. It is a bet that the people guarding defence systems, infrastructure and financial networks would rather trust the chip than build fortresses around it, and the test of that bet lies a year or more ahead, when samples reach the engineers who must decide.
AMD has unveiled a new family of chips built around a single, unsettling possibility: that someone will get hands on the silicon and attack it from below. The Versal TR line is meant for systems that handle sensitive information, and AMD says it is the first adaptive SoC or FPGA-based product with built-in protection against backside attacks.
The protection comes from a sensor-based die bonded to the main compute die, covering the whole underside of the device. If that protective layer is tampered with or removed, the chip will not boot. The devices extend the Versal AI Edge Gen 2 range and target defence, critical infrastructure, data centre networking and financial technology.
The pitch is simplicity. Organisations worried about physical attacks often build their own defences from custom enclosures and specialised chips. AMD argues that moving protection into the silicon removes much of that work. The three parts, the 2VE3358TR, 2VE3558TR and 2VE3858TR, each have a footprint-compatible standard counterpart, so teams can start development on existing parts and later switch with minimal effort.
AMD expects samples in the second half of 2027 and production in the first half of 2028. Whether customers will trade their familiar board-level protections for this integrated approach is the question that will settle its success.
AMD has announced a new family of chips built around a simple worry: someone getting physical access to the silicon and attacking it from underneath. The Versal tamper-resistant line, or Versal TR, is meant for systems that handle sensitive information, and AMD says it is the first adaptive SoC or FPGA-based product with built-in protection against attacks on the backside of the chip.
The mechanism is a sensor-based protection die bonded to the main compute die using 3D active-on-active technology. It covers the entire backside of the device. If the protection die is tampered with or removed, the chip will not boot.
The devices extend AMD's Versal AI Edge Series Gen 2 range and are aimed at defence, critical infrastructure, data centre networking and financial technology customers. The pitch is about cost and complexity. Organisations that worry about physical attacks often assemble their own protection from custom enclosures, application-specific chips and other board-level measures. AMD argues that folding the protection into the chip itself simplifies that work.
The underlying processing architecture is the one already used in the AI Edge family: Arm CPUs, AI Engines, programmable logic, hard IP and connectivity in a single package. AMD quotes peak figures of up to 229,000 DMIPS of scalar compute, up to 369 INT8 TOPS and up to 543,000 LUTs.
Beyond the backside layer, the chips carry a wider set of security features. Hardware acceleration for post-quantum cryptography has been expanded, with support for the Module-Lattice-Based Digital Signature Algorithm and the Stateless Hash-Based Digital Signature Algorithm. A hybrid boot flow allows multiple signature algorithms. AMD has updated the application security unit key vault and added a memory element aging sensor, intended as an extra safeguard for cryptographic keys.
Glitch detection is also changed. Glitch attacks try to disrupt a chip by manipulating its electrical conditions. AMD says the new devices pair updates to the existing Versal glitch detector with an additional orthogonal detector, including coverage for glitches that hit two voltage rails at the same time.
The range has three parts: the 2VE3358TR, 2VE3558TR and 2VE3858TR, offered as a common platform for customers with different performance and cost needs. Each has a footprint-compatible standard counterpart already available in the Versal AI Edge Series Gen 2 family. Customers can start development on those existing parts and later move to the tamper-resistant versions with minimal effort, without rerunning synthesis or place and route. That may suit organisations with long development cycles in regulated or security-sensitive markets.
Kirk Saban, corporate vice president of product, software and solutions at AMD Embedded, said protecting critical information demands continued innovation in silicon security. He described the line as bringing built-in protection against physical attacks together with high-performance heterogeneous compute in a commercial adaptive SoC.
AMD expects the first Versal TR devices to sample in the second half of 2027, with production planned for the first half of 2028. The open question is whether customers will adopt the integrated approach over the custom board-level protections they use now.
Citas Notables
AMD is bringing built-in protection against physical attacks together with high-performance heterogeneous compute in a commercial adaptive SoC, helping customers simplify the development of security-critical systems.— Kirk Saban, corporate vice president, AMD Embedded
Quieres la nota completa?
Lee el original en IT Brief Australia ↗