Keep the channel thin where it needs to be, add material only where current flows
At the frontier where physics meets engineering ambition, researchers at POSTECH in South Korea have resolved a paradox that has quietly constrained the semiconductor industry for years: the thinner a chip's channel, the harder it becomes for current to enter it. By selectively thickening only the points where electrons cross from metal into material, the team found a way to honor both demands at once — suppressing leakage without strangling flow. It is the kind of solution that does not defeat a constraint so much as sidestep it with precision, and its implications reach toward the three-dimensional chips that artificial intelligence increasingly requires.
- The semiconductor industry's push toward thinner channels — necessary to prevent current leakage in AI-era chips — was quietly generating a second crisis: contact resistance so severe it negated the gains.
- Every attempt to solve one side of the problem worsened the other, trapping engineers in a binary choice between leakage control and electrical efficiency.
- POSTECH's team broke the deadlock by applying a technique borrowed from silicon manufacturing — Raised Source and Drain — to selectively bulk up only the electrode contact zones of a tellurium transistor while leaving the four-nanometer channel untouched.
- The outcome was dramatic: contact resistance fell fifty-fold and on-state current surged more than seventeen times, even under extreme cold conditions of minus 196 degrees Celsius.
- Because the method relies on sputtering — a scalable, low-temperature process already embedded in chip fabrication — it is positioned to move from laboratory result to industrial reality, and to extend beyond tellurium to other ultra-thin materials.
The semiconductor industry has long operated under a quiet contradiction: the same thinness that makes a chip channel better at controlling electrons makes it worse at receiving them. As artificial intelligence and high-performance computing push for denser, more powerful architectures, engineers have increasingly looked to three-dimensional stacking — layering logic and memory vertically to shrink the distance data must travel. But building such structures demands materials that can withstand fabrication at temperatures below 400 degrees Celsius, and that requirement narrowed the field considerably.
Tellurium emerged as a strong candidate. It conducts electrons well, remains stable at room temperature, and tolerates low-heat processing. Its weakness was a narrow band gap that allowed current to leak even when a transistor was switched off. The fix was to shrink the channel — the electron pathway — to under five nanometers, thin enough to assert control over which electrons moved. But that solution carried a cost: at such scales, the energy barrier between metal electrode and semiconductor grew steep, producing contact resistance that throttled current and wasted power. Thinner meant less leakage and more resistance. Thicker meant the reverse. The two goals could not be reconciled — until they were.
Professor Byoung Hun Lee and his team at POSTECH adapted a technique from conventional silicon manufacturing called Raised Source and Drain. Rather than choosing a single thickness for the entire device, they deposited extra tellurium only at the source and drain — the zones where current enters and exits — while preserving a four-nanometer channel in between. The geometry gave electrons a wider path at the critical crossing points without compromising the channel's ability to suppress leakage.
The measured results were stark. Contact resistance fell from 97.5 kilohm-micrometers to 1.7 — a fifty-fold reduction. On-state current rose more than seventeen times, holding even at minus 196 degrees Celsius. The paradox had been dissolved not by new materials or exotic processes, but by spatial selectivity.
The technique's broader significance lies in its practicality. Sputtering — the deposition method used for the selective thickening — is already a standard, large-area, low-temperature process in semiconductor manufacturing. That means the approach scales, and it is not limited to tellurium. It could be applied across the growing family of two-dimensional and ultra-thin materials, offering the industry a viable path toward the next generation of three-dimensional integrated circuits.
The semiconductor industry faces a stubborn paradox: make the chips thinner and you solve one problem while creating another. Researchers at POSTECH, a South Korean university, have found a way to break that cycle—not by choosing between two bad options, but by being selective about where thickness matters.
The problem starts with the relentless push toward miniaturization. As artificial intelligence and high-performance computing demand more processing power, the bottleneck has shifted. It's no longer the raw speed of calculation. It's the distance between where logic happens and where memory lives. Every bit of data that travels between them costs time and energy. The solution gaining traction is to stack logic and memory vertically in three dimensions, compressing that distance. But building these structures requires materials that can survive the manufacturing process at temperatures below 400 degrees Celsius.
Tellurium emerged as a promising candidate. It moves electrons efficiently, stays stable at room temperature, and can be processed at low heat. There was one catch: its narrow band gap makes it leak current even when switched off. To stop that leakage, engineers had to shrink the channel—the path where electrons flow—to less than five nanometers thick. At that scale, they could control which electrons moved and which stayed put.
But thinner channels created a new trap. As the channel shrank, the barrier between the metal electrode and the semiconductor grew taller. Electrons had to climb a steeper energy hill to cross from the metal into the channel. The result was contact resistance—a chokepoint that slowed current flow and wasted power. Researchers could reduce leakage by going thinner, or they could reduce resistance by going thicker. They could not do both.
The POSTECH team, led by Professor Byoung Hun Lee, borrowed a technique from silicon manufacturing called Raised Source and Drain. The idea is deceptively simple: keep the main channel thin where it needs to be, but add extra material only at the points where current enters and exits. They deposited additional tellurium at the source and drain—the electrode contact zones—while maintaining a four-nanometer channel in between. Current had a thicker path to flow through at the critical junctions, but the channel itself remained thin enough to suppress leakage.
The results were striking. Contact resistance dropped by a factor of fifty, from 97.5 kilohm-micrometers down to 1.7. When the device was fully switched on, current flow increased more than seventeen times over, even at the extreme temperature of minus 196 degrees Celsius. The team had solved the paradox: they achieved both low resistance and high performance in an ultra-thin structure.
What makes this breakthrough practical is how it gets built. The selective thickening uses sputtering, a large-area, low-temperature deposition process already used in semiconductor manufacturing. That means the technique scales. It can be applied not just to tellurium but to other two-dimensional and ultra-thin materials. For an industry racing to build the next generation of three-dimensional integrated circuits, that scalability matters. The approach addresses a fundamental constraint that has limited device performance for years, and it does so with a method factories can actually use.
Notable Quotes
We have broken through the chronic dilemma of ultra-thin semiconductors—where thinner channels traditionally resulted in higher resistance—with a novel band engineering approach called localized thickness control.— Professor Byoung Hun Lee, POSTECH Department of Electrical Engineering
The Hearth Conversation Another angle on the story
Why does making a semiconductor thinner create a resistance problem in the first place?
When you shrink the channel to suppress leakage current, you're creating a taller energy barrier—what physicists call a Schottky barrier—between the metal electrode and the semiconductor. Electrons have to climb that barrier to flow through. The thinner you go, the harder that climb becomes.
So the solution is just to add material back in some places. Why didn't anyone think of that before?
They did, in silicon. But tellurium is different. The trick was figuring out exactly where to add it and how much. You need the channel itself to stay thin to control leakage, but the contact zones need to be thick enough for current to flow freely. It's about precision placement, not just adding bulk.
Does this only work for tellurium, or is it broader?
Tellurium was the test case, but the principle applies to any ultra-thin semiconductor material. As long as you have the same trade-off between leakage and resistance, selective thickening at the contacts should help. That's why the researchers think this becomes a platform technology.
What changes for manufacturers?
They can use sputtering, which they already have. No new equipment, no exotic processes. That's what makes it scalable. You can apply this to mass production without reinventing the factory.
And this matters for AI because?
AI systems need to move enormous amounts of data between logic and memory. Every nanosecond of delay, every watt of wasted power, adds up across billions of transistors. Three-dimensional stacking compresses that distance, but you need materials that work at low temperatures and don't leak current. This solves both problems at once.