Reinventing how chips are built, not just making them smaller
At the frontier where physics and engineering converge, IBM has announced a chip architecture so small it is measured in individual atoms — a 0.7 nanometre design that stacks transistors vertically like a hundred-storey tower rather than spreading them across a flat plain. The announcement arrives at a moment when the semiconductor industry's long-held rhythm of miniaturisation is running out of horizontal space, and the question of how computing continues to grow more powerful without growing larger has become urgent. IBM's answer is architectural imagination, though the distance between a laboratory prototype and a chip in a consumer's hand remains, as ever, a journey measured in years and unsolved problems.
- The semiconductor industry's foundational law — that transistor counts double every two years — is colliding with the hard boundary of atomic physics, leaving engineers searching for a new direction.
- IBM's 0.7nm NanoStack prototype packs 100 billion transistors onto a fingernail-sized chip by building upward in three dimensions, outpacing rivals Samsung and Intel whose comparable 3D efforts reach only half the density.
- Heat trapped inside densely stacked layers and transistors that refuse to switch off cleanly are the two concrete engineering crises standing between this prototype and a manufacturable product.
- IBM has acknowledged that production is still years away — a familiar caveat, given that its 2021 announcement of 2nm technology only now sees chips reaching commercial shelves.
- The trajectory points toward a computing landscape of dramatically greater performance and energy efficiency, but the road there runs through engineering problems that do not yet have clear solutions.
IBM announced this week the design of a chip operating at 0.7 nanometres — a scale so fine it is described in individual atoms, and well below the industry's current 2nm standard. In laboratory conditions, the prototype fitted 100 billion transistors onto a piece of silicon the size of a fingernail, running 50 percent faster and consuming 30 percent less power than IBM's existing 2nm chips.
The breakthrough is less about making transistors smaller and more about rethinking where they go. Rather than arranging transistors side by side across a flat silicon surface — a method approaching its physical limits — IBM's NanoStack architecture layers them vertically in three dimensions. Jay Gambetta of IBM Research described it as a fundamental reimagining of chip construction. Professor Alan Woodward of Surrey University put it plainly: traditional chip design builds houses across a city; IBM is building a hundred-storey skyscraper, while closest rivals Samsung and Intel are working on structures of thirty to fifty storeys.
The engineering obstacles, however, are formidable. Heat generated by tightly stacked transistors has nowhere to dissipate, and ultra-thin separating layers can cause transistors to fail to switch off correctly — a malfunction that cascades through the entire chip. Neither problem has a clear solution yet.
IBM has been candid that production deployment remains years away. The company made similarly striking claims when it unveiled its 2nm chip in 2021, and that technology is only now entering commercial products. The gap between a working prototype and a chip inside a data centre or a consumer device is wide, and crossing it will demand solving problems that currently exist only as warnings on the horizon.
IBM announced this week that it has designed a chip smaller than anything the semiconductor industry has produced before—a breakthrough the company says could reshape computing for the next decade, even as engineers caution that turning the design into actual products will take years of work.
The new chip measures 0.7 nanometres, a unit so small it describes distances measured in individual atoms. To put that in perspective, the current standard across the industry sits at around 2 nanometres. IBM's design would allow manufacturers to pack 100 billion transistors onto a piece of silicon the size of a fingernail. In laboratory tests, the prototype ran 50 percent faster than IBM's existing 2-nanometre chips and consumed 30 percent less power.
Transistors are the fundamental switches that make all modern electronics work. Every smartphone, laptop, and data centre server relies on billions of them working in concert. For decades, the industry has followed a predictable pattern: the number of transistors that fit on a chip has doubled roughly every two years, a phenomenon known as Moore's Law. But that trajectory is hitting a wall. With transistors already measured in atoms, there is simply no more room to make them smaller by spreading them out horizontally across the silicon surface.
IBM's solution is architectural rather than purely miniaturization. Instead of trying to squeeze more transistors side by side, the company has designed a system that stacks transistors vertically, layering them on top of each other in three dimensions. Jay Gambetta, who directs IBM Research, called the approach—branded NanoStack—a landmark moment. He emphasized that the innovation was not merely about making transistors smaller, but fundamentally rethinking how chips are constructed to achieve both power and efficiency gains.
Professor Alan Woodward, a computer scientist at Surrey University, offered a useful analogy: if traditional chip design is like building houses across a city, IBM's approach is like constructing a 100-storey skyscraper. He noted that IBM's closest competitors, Samsung and Intel, are working on similar 3D strategies but have achieved designs comparable to 30 to 50-storey buildings. "I think it's fair to say IBM's proposals are the most ambitious," Woodward said.
But ambition and execution are different things. The engineering challenges are substantial. Heat is the first problem: as transistors work, they generate warmth, and in a densely stacked structure, that heat has nowhere to go. The second challenge is more subtle. When the layers separating transistors become too thin, the transistors sometimes fail to switch off when they should, causing the entire chip to malfunction. These are not theoretical concerns—they are the practical obstacles standing between a working prototype and a chip that can be manufactured at scale.
IBM itself acknowledged that several years will pass before this technology reaches production. The company made similar claims when it unveiled its 2-nanometre technology in 2021, touting comparable performance and efficiency gains. That chip is only now beginning to appear in commercial products. The gap between laboratory success and real-world deployment in consumer devices or data centres remains substantial, and the path forward will require solving problems that do not yet have clear solutions.
Citações Notáveis
With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency.— Jay Gambetta, IBM Research director
IBM's NanoStack is like proposing a 100-storey skyscraper, while Samsung and Intel are closer to 30-50 storey buildings with their own 3D chip work.— Professor Alan Woodward, Surrey University
A Conversa do Hearth Outra perspectiva sobre a história
Why does IBM think they can stack transistors vertically when heat and switching problems have plagued 3D designs for years?
They've engineered what they call NanoStack—essentially a way to manage the heat and electrical isolation between layers. But the honest answer is they don't fully know yet. That's why it's years away from production.
If this works, what changes for someone using a phone or laptop?
Everything becomes faster and lasts longer on a single charge. A device with 100 billion transistors in a fingernail-sized space could do vastly more computation with less power draw. But that's the if.
Why does Moore's Law matter so much that IBM is willing to take on these risks?
Because the alternative is stagnation. You can't make transistors much smaller horizontally—you're already at the atomic scale. If you can't pack more transistors onto chips, computing power plateaus. AI, data centres, everything that depends on exponential growth stops.
So this is really about keeping the entire tech industry moving forward?
Exactly. IBM, Samsung, Intel—they're all racing to solve the same problem because whoever cracks 3D stacking at scale wins the next era of computing.
What's the most likely thing that could go wrong?
Heat management or the switching problem could prove unsolvable at this scale. Or manufacturing could be so expensive that it's not economically viable. Both have killed promising chip designs before.